US US11187747B2

Inspection system and malfunction analysis/prediction method for inspection …

Publication no.

US11187747B2
Priority date
2017-03-02
Filing date
2018-01-30
Published
2021-11-30
Granted
2021-11-30
Assignee
Tokyo Electron Limited
Inventor

Tetsuya Kagami

Abstract

34 b may be pogo pins. The inspection circuit boards 33 are configured to apply electrical signals to the devices formed on the wafer W depending on various test items. The tester control unit 35 includes a main controller having a CPU configured to control the respective components of the tester

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